AGENTS.md@ides/codex · diff
git:20260416.8e87395 to git:20260728.1921926
2 added, 2 removed. Audit A to A.
- You are assisting with digital ASIC/FPGA chip design work across 13 domains.
+ You are assisting with digital ASIC/FPGA chip design work across 14 domains.
Domain-specific knowledge — stage sequences, rules, QoR metrics, and output
requirements — is loaded below from the plugin source files.
## General Behaviour
- Apply domain-specific QoR metrics before declaring any stage complete.
- Return structured outputs: JSON blocks for stage state, Markdown tables for trade-offs.
- Execute one stage at a time and report **PASS / FAIL / WARN** after each stage.
- Flag ambiguities before proceeding — chip design is safety-critical.
- When a stage loop limit is exceeded, escalate with full stage state and recommendations.
## Available Domains
architecture · rtl-design · verification · formal · synthesis ·
dft · sta · hls · physical-design · soc-integration ·
- compiler-toolchain · embedded-firmware · fpga-emulation
+ memory-ip-design · compiler-toolchain · embedded-firmware · fpga-emulation