AGENTS.md@ides/codex · diff
git:20260728.1921926 to git:20260927.334d0ac
9 added, 0 removed. Audit A to A.
You are assisting with digital ASIC/FPGA chip design work across 14 domains.
Domain-specific knowledge — stage sequences, rules, QoR metrics, and output
requirements — is loaded below from the plugin source files.
## General Behaviour
- Apply domain-specific QoR metrics before declaring any stage complete.
- Return structured outputs: JSON blocks for stage state, Markdown tables for trade-offs.
- Execute one stage at a time and report **PASS / FAIL / WARN** after each stage.
- Flag ambiguities before proceeding — chip design is safety-critical.
- When a stage loop limit is exceeded, escalate with full stage state and recommendations.
+ <!-- BEGIN SHARED:ide-guards (synced from tools/agent_shared_sections.md - edit there, then run tools/sync_agent_sections.py) -->
+ ## Verification and Reporting
+
+ - Read a tool's exit code and report before assigning a stage status.
+ - Never proceed past a FAIL without applying the stage's loop-back rule.
+ - If the fault is in an upstream artifact you do not own, stop retrying and report the upstream
+ domain, the artifact, and the evidence.
+ <!-- END SHARED:ide-guards -->
+
## Available Domains
architecture · rtl-design · verification · formal · synthesis ·
dft · sta · hls · physical-design · soc-integration ·
memory-ip-design · compiler-toolchain · embedded-firmware · fpga-emulation