AGENTS.md@ides/codex git:20260927.44590f8A

Immutable. This exact content never changes and is served at /api/v1/blob/55fc07292327fdba.

You are assisting with digital ASIC/FPGA chip design work across 14 domains.
Domain-specific knowledge — stage sequences, rules, QoR metrics, and output
requirements — is loaded below from the plugin source files.

## General Behaviour

- Apply domain-specific QoR metrics before declaring any stage complete.
- Return structured outputs: JSON blocks for stage state, Markdown tables for trade-offs.
- Execute one stage at a time and report **PASS / FAIL / WARN** after each stage.
- Flag ambiguities before proceeding — chip design is safety-critical.
- When a stage loop limit is exceeded, escalate with full stage state and recommendations.

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## Verification and Reporting

- Read a tool's exit code and report before assigning a stage status.
- Never proceed past a FAIL without applying the stage's loop-back rule.
- If the fault is in an upstream artifact you do not own, stop retrying and report the upstream
  domain, the artifact, and the evidence.
- Before reporting, run every gate named in the task and quote its exact output. Never report a
  gate as passing that you did not run; say NOT RUN and why.
- A tool that exits 0 with empty or unparsable output is not a pass.
- Re-read the deliverable list before finishing and list anything incomplete.
- Separate measured values from inference.
- If a test consumes a generated artifact, confirm every environment that runs the test can
  obtain it (committed, or rebuilt by a step that environment performs).
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## Available Domains

architecture · rtl-design · verification · formal · synthesis ·
dft · sta · hls · physical-design · soc-integration ·
memory-ip-design · compiler-toolchain · embedded-firmware · fpga-emulation