ams-sim git:20260613.86cacb4A

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---
name: ams-sim
description: Plan and run analog / mixed-signal simulations — DC op, AC, transient, Monte Carlo, corner sweeps, PSRR/CMRR, noise — using ngspice, Xyce, Spectre, or HSPICE, and triage the results. Use when the user says "SPICE", "ngspice", "Monte Carlo", "corner simulation", "analog sim", "AC analysis", "transient", "PSRR", "CMRR", "noise analysis".
---

# AMS Sim

Analog blocks must be verified across process corners, temperature, voltage, and mismatch. This skill plans the testbench matrix, generates the simulator decks, and triages results.

## When to use

- After `/analog-sizing` produces a schematic
- After `/analog-layout` + extraction (post-layout)
- When mismatching is the suspected failure mode (Monte Carlo)
- Mixed-signal co-simulation with a digital controller (ngspice + Verilog-A, or Spectre APS)

## Inputs

1. Schematic / netlist (`.sp`, `.cir`, `.scs`)
2. Device models from PDK (`.lib` / `.scs`)
3. Specs to verify (gain, BW, PSRR, CMRR, noise, slew, settling, offset)
4. Corner definition (FF/SS/TT/FS/SF × temp × supply)
5. Monte Carlo N (typical 500–5000 runs)

## Analysis matrix

| Analysis | Purpose |
|---|---|
| `.op` | DC operating point, bias validation |
| `.dc` | Sweeps (supply, input, parameter) |
| `.ac` | Gain, bandwidth, phase margin |
| `.tran` | Settling, slew, large-signal |
| `.noise` | Input-referred noise, SNR |
| `.pss` / `.pac` / `.pnoise` | Periodic steady-state (for RF / SC circuits) |
| `.mc` | Monte Carlo mismatch + process |

The spec → required-analysis-subset mapping in this table is a frozen
lookup, **enforced by `programs/ams_analysis_select.py`** — do NOT pick
the analysis set by hand (two agents would otherwise pick different /
incomplete subsets for the same spec list). Run it on the block's
`spec.json` (or the project dir to scan `analog/*/spec.json`) and use
the emitted `analyses` set:

```bash
python3 programs/ams_analysis_select.py <block>/spec.json
# -> {"analyses": [".op", ".ac", ".tran", ".noise"], "mapping": [...]}
```

It always selects `.op` (bias validation) when ≥1 measurable spec is
present, adds `.mc` whenever any spec declares a mismatch / σ / yield
concern, and FAILs honestly (exit 1) when a spec carries no recognizable
measurable metric. Agent judgment is only needed to override an
ambiguous / custom spec key the table does not recognize.

## Workflow

1. Pick the analysis subset — **enforced by `programs/ams_analysis_select.py`** (see Analysis matrix)
2. Build deck with corner + MC sweeps
3. Run (ngspice / Xyce / Spectre / HSPICE)
4. Extract measurements via `.meas` statements — generated by `programs/analog_meas_from_spec_gen.py`
5. Tabulate corners × MC yield vs spec — **enforced by `programs/corner_yield_vs_spec_check.py`** (re-derives per-corner / per-spec PASS/FAIL from `spec.json` min/max limits + reports the worst, smallest-margin corner) and **`programs/analog_corner_sweep_check.py`** (gates ≥9-corner PVT count + all-spec-pass). Do NOT hand-tabulate the yield table — quote these programs' verdicts.
6. Flag failing corners — the worst corner is the `worst_corner` field from `corner_yield_vs_spec_check.py`; PVT-coverage gaps are classified by **`programs/corner_coverage_audit.py`**. Propose sizing or layout changes (agent judgment).
7. Hand off to re-sizing loop

## Output format

- `sim/<block>.sp` (or equivalent) — simulator deck
- `sim/<block>_results.md`:
  - Spec table with pass/fail per corner — populated from `corner_yield_vs_spec_check.py` (per-corner / per-spec PASS/FAIL re-derived from `spec.json` limits), not graded by eye
  - MC yield percentage per spec — gated by `analog_corner_sweep_check.py`
  - Sensitivity list (which device / parameter dominates) — agent judgment
  - Suggested fixes — agent judgment

## Tool prerequisites

Open source: ngspice (https://ngspice.sourceforge.io/), Xyce. Commercial: Cadence Spectre, Synopsys HSPICE, Silvaco SmartSpice.

## Technical basis

Pelgrom mismatch model, corner methodology from PDK, Monte Carlo with correlated process parameters. Mixed-signal co-sim per Verilog-AMS / Verilog-A standards.

## Handoff

- Failing corners → `/analog-sizing` (re-size)
- Layout-driven failures → `/analog-layout`
- Model issues → escalate to PDK team

## Compliance gate (mandatory)

After producing your output, save it to a file and run:

```bash
python3 plugins/vibe-ic/_shared/skill_compliance_check.py \
    --requirements plugins/vibe-ic/skills/ams-sim/compliance.yaml \
    <your_output_file>
```

Exit 0 = PASS, exit 1 = FAIL with specific missing elements listed.
`compliance.yaml` in the corresponding skill directory enumerates
every required element of your output: section headers, metadata fields,
handoff lines, tool invocations.

**Your task is not complete until the audit returns PASS.** Missing
elements are the single largest source of skill-execution non-determinism
across different agents.