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hdl-tools/digital-chip-design-agents

18 instruction files for AI agents, collected from hdl-tools/digital-chip-design-agents. Install any of them at an exact version with mdr add hdl-tools/digital-chip-design-agents/<name>.

AGENTS.md@ides/codex AGENTS.md file
hdl-tools/digital-chip-design-agents · ides/codex/AGENTS.md
git:20261003.db76060 · audit A · 220 stars
architecture SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/architecture/skills/architecture/SKILL.md · Microarchitecture exploration, PPA estimation, risk assessment, and architecture sign-off for digital chip design. Use…
v1.0.0 · audit A · 220 stars
compiler-toolchain SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/compiler/skills/compiler-toolchain/SKILL.md · Compiler toolchain development for custom processor ISAs — LLVM/GCC backend, assembler, linker scripts, runtime…
v1.0.0 · audit A · 220 stars
dft SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/dft/skills/dft/SKILL.md · Design for Test — scan architecture planning, scan insertion, ATPG pattern generation, MBIST for embedded memories, and…
v1.0.0 · audit A · 220 stars
embedded-firmware SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/firmware/skills/embedded-firmware/SKILL.md · Embedded firmware and device drivers — BSP development, peripheral driver implementation (UART, SPI, I2C, GPIO, DMA…
v1.0.0 · audit A · 220 stars
formal-verification SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/formal/skills/formal-verification/SKILL.md · Formal property verification (FPV) and logical equivalence checking (LEC). Use when proving design properties…
v1.0.0 · audit A · 220 stars
fpga-emulation SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/fpga/skills/fpga-emulation/SKILL.md · FPGA prototyping — ASIC-to-FPGA RTL adaptation, multi-FPGA partitioning, synthesis and timing closure on FPGA, hardware…
v1.0.0 · audit A · 220 stars
hls SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/hls/skills/hls/SKILL.md · High-Level Synthesis — C/C++ algorithm analysis, HLS directive optimisation, synthesis execution, and co-simulation…
v1.0.0 · audit A · 220 stars
infrastructure SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/infrastructure/skills/infrastructure/SKILL.md · EDA tool detection, wrapper deployment, and MCP configuration for digital chip design environments. Use when setting up…
v1.0.0 · audit B · 220 stars
memory-keeper SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/infrastructure/skills/memory-keeper/SKILL.md · Distil accumulated experience records (experiences.jsonl) into updated domain knowledge summaries (knowledge.md) for…
v1.0.0 · audit A · 220 stars
memory-ip-design SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/memory-ip/skills/memory-ip-design/SKILL.md · Embedded memory IP design — SRAM/register-file/ROM requirements capture, memory compiler and macro selection, array…
v1.0.0 · audit A · 220 stars
pipeline-orchestration SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/meta/skills/pipeline-orchestration/SKILL.md · Cross-domain loop orchestration for the chip design pipeline. Provides the fix_request protocol, iteration-cap logic…
v1.0.0 · audit A · 220 stars
physical-design SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/pd/skills/physical-design/SKILL.md · Full physical design flow — floorplan, placement, clock tree synthesis, routing, timing optimisation, power…
v1.0.0 · audit A · 220 stars
rtl-design SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/rtl-design/skills/rtl-design/SKILL.md · SystemVerilog RTL design — module planning, coding standards enforcement, lint checking, CDC/RDC analysis, and…
v1.0.0 · audit A · 220 stars
soc-integration SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/soc/skills/soc-integration/SKILL.md · SoC IP integration — IP procurement and qualification, IP configuration, bus fabric setup, top-level RTL integration…
v1.0.0 · audit A · 220 stars
sta SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/sta/skills/sta/SKILL.md · Static timing analysis — multi-corner constraint validation, setup and hold analysis, timing exception review, and ECO…
v1.0.0 · audit A · 220 stars
logic-synthesis SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/synthesis/skills/logic-synthesis/SKILL.md · Logic synthesis from RTL to gate-level netlist — SDC constraint validation, compile and optimisation strategy, netlist…
v1.0.0 · audit A · 220 stars
functional-verification SKILL.md skill
hdl-tools/digital-chip-design-agents · plugins/verification/skills/functional-verification/SKILL.md · UVM-based functional verification — testbench architecture, test planning, directed and constrained-random stimulus…
v1.0.0 · audit A · 220 stars

Source

github.com/hdl-tools/digital-chip-design-agents · 220 stars · license MIT · pushed 2026-10-19