27 instruction files for AI agents, collected from nguyenquanicd/vlsit_codex_claude_skills. Install any of them at an exact version with mdr add nguyenquanicd/vlsit_codex_claude_skills/<name>.
vlsit-asic-ip-microspec SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .agents/skills/vlsit-asic-ip-microspec/SKILL.md · Discuss and write an ASIC IP micro-architecture specification in the VLSIT template as Markdown with TeX math…
git:20261108.53407f2 · audit B · 24 stars
vlsit-create-skill SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .agents/skills/vlsit-create-skill/SKILL.md · Create a new agent skill in the house format (SKILL.md workflow, rule.md with numbered rules, reference/ and scripts/…
git:20261108.9a075f0 · audit A · 24 stars
vlsit-opencore-ip-downloader SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .agents/skills/vlsit-opencore-ip-downloader/SKILL.md · Search OpenCores and its linked public repositories for open-source hardware IP, download each project with its RTL…
git:20261108.9a075f0 · audit A · 24 stars
vlsit-rtl-generator SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .agents/skills/vlsit-rtl-generator/SKILL.md · Generate synthesizable SystemVerilog RTL from a design specification written in the VLSIT ASIC IP template, or modify…
git:20261108.53407f2 · audit B · 24 stars
vlsit-rtl-hierarchy-diagram SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .agents/skills/vlsit-rtl-hierarchy-diagram/SKILL.md · Analyze existing Verilog or SystemVerilog RTL to trace module hierarchy, functional relationships, and protocol…
git:20261108.9a075f0 · audit A · 24 stars
vlsit-rtl-spec-change-implementer SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .agents/skills/vlsit-rtl-spec-change-implementer/SKILL.md · Analyze existing RTL against an optional prior specification and a requested new feature, present a minimal-change plan…
git:20261108.53407f2 · audit A · 24 stars
vlsit-spec-to-docx SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .agents/skills/vlsit-spec-to-docx/SKILL.md · Convert a Markdown design specification into a filled copy of the VLSIT IP Microarchitecture Specification DOCX…
git:20261108.9a075f0 · audit A · 24 stars
vlsit-vhdl-to-systemverilog SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .agents/skills/vlsit-vhdl-to-systemverilog/SKILL.md · Convert complete VHDL RTL designs into readable, synthesizable SystemVerilog under the bundled VLSIT coding rules…
git:20261108.9a075f0 · audit A · 24 stars
vlsit-wavedrom-waveform SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .agents/skills/vlsit-wavedrom-waveform/SKILL.md · Draw timing waveforms with the bundled offline WaveDrom from a short request, a VCD file (whole file or a time window)…
git:20261018.29a18b0 · audit B · 24 stars
vlsit-asic-ip-microspec SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .claude/skills/vlsit-asic-ip-microspec/SKILL.md · Discuss and write an ASIC IP micro-architecture specification in the VLSIT template as Markdown with TeX math…
git:20261108.53407f2 · audit B · 24 stars
vlsit-create-skill SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .claude/skills/vlsit-create-skill/SKILL.md · Create a new agent skill in the house format (SKILL.md workflow, rule.md with numbered rules, reference/ and scripts/…
git:20261108.9a075f0 · audit A · 24 stars
vlsit-opencore-ip-downloader SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .claude/skills/vlsit-opencore-ip-downloader/SKILL.md · Search OpenCores and its linked public repositories for open-source hardware IP, download each project with its RTL…
git:20261108.9a075f0 · audit A · 24 stars
vlsit-rtl-generator SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .claude/skills/vlsit-rtl-generator/SKILL.md · Generate synthesizable SystemVerilog RTL from a design specification written in the VLSIT ASIC IP template, or modify…
git:20261108.53407f2 · audit B · 24 stars
vlsit-rtl-hierarchy-diagram SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .claude/skills/vlsit-rtl-hierarchy-diagram/SKILL.md · Analyze existing Verilog or SystemVerilog RTL to trace module hierarchy, functional relationships, and protocol…
git:20261108.9a075f0 · audit A · 24 stars
vlsit-rtl-spec-change-implementer SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .claude/skills/vlsit-rtl-spec-change-implementer/SKILL.md · Analyze existing RTL against an optional prior specification and a requested new feature, present a minimal-change plan…
git:20261108.53407f2 · audit A · 24 stars
vlsit-spec-to-docx SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .claude/skills/vlsit-spec-to-docx/SKILL.md · Convert a Markdown design specification into a filled copy of the VLSIT IP Microarchitecture Specification DOCX…
git:20261108.9a075f0 · audit A · 24 stars
vlsit-vhdl-to-systemverilog SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .claude/skills/vlsit-vhdl-to-systemverilog/SKILL.md · Convert complete VHDL RTL designs into readable, synthesizable SystemVerilog under the bundled VLSIT coding rules…
git:20261108.9a075f0 · audit A · 24 stars
vlsit-wavedrom-waveform SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .claude/skills/vlsit-wavedrom-waveform/SKILL.md · Draw timing waveforms with the bundled offline WaveDrom from a short request, a VCD file (whole file or a time window)…
git:20261018.29a18b0 · audit B · 24 stars
vlsit-asic-ip-microspec SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .dsh/skills/vlsit-asic-ip-microspec/SKILL.md · Discuss and write an ASIC IP micro-architecture specification in the VLSIT template as Markdown with TeX math…
git:20261108.53407f2 · audit B · 24 stars
vlsit-create-skill SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .dsh/skills/vlsit-create-skill/SKILL.md · Create a new agent skill in the house format (SKILL.md workflow, rule.md with numbered rules, reference/ and scripts/…
git:20261108.9a075f0 · audit A · 24 stars
vlsit-opencore-ip-downloader SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .dsh/skills/vlsit-opencore-ip-downloader/SKILL.md · Search OpenCores and its linked public repositories for open-source hardware IP, download each project with its RTL…
git:20261108.9a075f0 · audit A · 24 stars
vlsit-rtl-generator SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .dsh/skills/vlsit-rtl-generator/SKILL.md · Generate synthesizable SystemVerilog RTL from a design specification written in the VLSIT ASIC IP template, or modify…
git:20261108.53407f2 · audit B · 24 stars
vlsit-rtl-hierarchy-diagram SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .dsh/skills/vlsit-rtl-hierarchy-diagram/SKILL.md · Analyze existing Verilog or SystemVerilog RTL to trace module hierarchy, functional relationships, and protocol…
git:20261108.9a075f0 · audit A · 24 stars
vlsit-rtl-spec-change-implementer SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .dsh/skills/vlsit-rtl-spec-change-implementer/SKILL.md · Analyze existing RTL against an optional prior specification and a requested new feature, present a minimal-change plan…
git:20261108.53407f2 · audit A · 24 stars
vlsit-spec-to-docx SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .dsh/skills/vlsit-spec-to-docx/SKILL.md · Convert a Markdown design specification into a filled copy of the VLSIT IP Microarchitecture Specification DOCX…
git:20261108.9a075f0 · audit A · 24 stars
vlsit-vhdl-to-systemverilog SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .dsh/skills/vlsit-vhdl-to-systemverilog/SKILL.md · Convert complete VHDL RTL designs into readable, synthesizable SystemVerilog under the bundled VLSIT coding rules…
git:20261108.9a075f0 · audit A · 24 stars
vlsit-wavedrom-waveform SKILL.md skill
nguyenquanicd/vlsit_codex_claude_skills · .dsh/skills/vlsit-wavedrom-waveform/SKILL.md · Draw timing waveforms with the bundled offline WaveDrom from a short request, a VCD file (whole file or a time window)…
git:20261108.9a075f0 · audit B · 24 stars