chipweaver/veripower

14 instruction files for AI agents, collected from chipweaver/veripower. Install any of them at an exact version with mdr add chipweaver/veripower/<name>.

CLAUDE.md@.claude CLAUDE.md file
chipweaver/veripower · .claude/CLAUDE.md
git:20261012.943a65c · audit B · 10 stars
AGENTS.md AGENTS.md file
chipweaver/veripower · AGENTS.md
git:20261019.238fae0 · audit A · 10 stars
brainstorm SKILL.md skill
chipweaver/veripower · skills/brainstorm/SKILL.md · Use when brainstorming a new module's requirements and architecture into a brainstorm.md, one way to write the intent…
git:20260920.095d122 · audit A · 10 stars
design-flow SKILL.md skill
chipweaver/veripower · skills/design-flow/SKILL.md · Use when progressing IC design through stages, checking module status, or routing rework decisions; not for…
git:20261012.6f764c1 · audit A · 10 stars
env-precheck SKILL.md skill
chipweaver/veripower · skills/env-precheck/SKILL.md · Use when checking whether this machine's Python, EDA tools and licenses can actually run VeriPower's stages; not for…
git:20260907.781745f · audit A · 10 stars
lint-cdc SKILL.md skill
chipweaver/veripower · skills/lint-cdc/SKILL.md · Check RTL lint and clock-domain crossings with SpyGlass, evaluate violations and justified waivers, and close the…
git:20260920.095d122 · audit A · 10 stars
power-analysis SKILL.md skill
chipweaver/veripower · skills/power-analysis/SKILL.md · Build and check power experiments, calculate averaged gate-level power with SAIF and PT-PX, and assess the results…
git:20260919.cdf15ac · audit A · 10 stars
rtl-design SKILL.md skill
chipweaver/veripower · skills/rtl-design/SKILL.md · Use when writing or modifying RTL and its file/constraint annotations, reviewing implementation against requirements…
git:20260920.095d122 · audit A · 10 stars
simulation-plan SKILL.md skill
chipweaver/veripower · skills/simulation-plan/SKILL.md · Use when generating or evolving a module's verification strategy, testpoints, TB scaffold and power measurement plan…
git:20260920.095d122 · audit A · 10 stars
simulation-triage SKILL.md skill
chipweaver/veripower · skills/simulation-triage/SKILL.md · Diagnose a failed verification run from requirements, implementation and experimental evidence, and identify the repair…
git:20260920.095d122 · audit A · 10 stars
simulation SKILL.md skill
chipweaver/veripower · skills/simulation/SKILL.md · Implement, review and run a module's functional testbench, diagnose verification failures and assess coverage; not for…
git:20260920.095d122 · audit A · 10 stars
specification SKILL.md skill
chipweaver/veripower · skills/specification/SKILL.md · Establish requirements, design decisions, interfaces, clocks and constraints from the delivered intent, or revise them…
git:20260919.cdf15ac · audit A · 10 stars
synthesis SKILL.md skill
chipweaver/veripower · skills/synthesis/SKILL.md · Establish the synthesized implementation, its constraints and measurements, and assess them against the task's…
git:20260920.095d122 · audit A · 10 stars
timing-analysis SKILL.md skill
chipweaver/veripower · skills/timing-analysis/SKILL.md · Assess post-synthesis setup and hold timing with PrimeTime and determine what the evidence establishes under the task's…
git:20260920.095d122 · audit A · 10 stars

Source

github.com/chipweaver/veripower · 10 stars · license MIT · pushed 2026-10-19