chipweaver/veripower

13 agent markdown files indexed from chipweaver/veripower. Install any of them pinned to an exact hash with mdr add chipweaver/veripower/<name>.

CLAUDE.md claude
chipweaver/veripower · CLAUDE.md
git:20260920.b97bd0b · audit A · 6 stars
brainstorm skill
chipweaver/veripower · skills/brainstorm/SKILL.md · Use when brainstorming a new module's requirements and architecture into a brainstorm.md, one way to write the intent…
git:20260920.095d122 · audit A · 6 stars
design-flow skill
chipweaver/veripower · skills/design-flow/SKILL.md · Use when progressing IC design through stages, checking module status, or routing rework decisions; not for…
git:20260920.095d122 · audit A · 6 stars
env-precheck skill
chipweaver/veripower · skills/env-precheck/SKILL.md · Use when checking whether this machine's Python, EDA tools and licenses can actually run VeriPower's stages; not for…
git:20260907.781745f · audit A · 6 stars
lint-cdc skill
chipweaver/veripower · skills/lint-cdc/SKILL.md · Check RTL lint and clock-domain crossings with SpyGlass, evaluate violations and justified waivers, and close the…
git:20260920.095d122 · audit A · 6 stars
power-analysis skill
chipweaver/veripower · skills/power-analysis/SKILL.md · Build and check power experiments, calculate averaged gate-level power with SAIF and PT-PX, and assess the results…
git:20260919.cdf15ac · audit A · 6 stars
rtl-design skill
chipweaver/veripower · skills/rtl-design/SKILL.md · Use when writing or modifying RTL and its file/constraint annotations, reviewing implementation against requirements…
git:20260920.095d122 · audit A · 6 stars
simulation-plan skill
chipweaver/veripower · skills/simulation-plan/SKILL.md · Use when generating or evolving a module's verification strategy, testpoints, TB scaffold and power measurement plan…
git:20260920.095d122 · audit A · 6 stars
simulation-triage skill
chipweaver/veripower · skills/simulation-triage/SKILL.md · Diagnose a failed verification run from requirements, implementation and experimental evidence, and identify the repair…
git:20260920.095d122 · audit A · 6 stars
simulation skill
chipweaver/veripower · skills/simulation/SKILL.md · Implement, review and run a module's functional testbench, diagnose verification failures and assess coverage; not for…
git:20260920.095d122 · audit A · 6 stars
specification skill
chipweaver/veripower · skills/specification/SKILL.md · Establish requirements, design decisions, interfaces, clocks and constraints from the delivered intent, or revise them…
git:20260919.cdf15ac · audit A · 6 stars
synthesis skill
chipweaver/veripower · skills/synthesis/SKILL.md · Establish the synthesized implementation, its constraints and measurements, and assess them against the task's…
git:20260920.095d122 · audit A · 6 stars
timing-analysis skill
chipweaver/veripower · skills/timing-analysis/SKILL.md · Assess post-synthesis setup and hold timing with PrimeTime and determine what the evidence establishes under the task's…
git:20260920.095d122 · audit A · 6 stars

Source

github.com/chipweaver/veripower · 6 stars · license MIT · pushed 2026-09-20